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3rd IEEE International Workshop on Reliability Aware System Design and Test
(In conjunction with the International Conference on VLSI Design)
(RASDAT 2012)

January 7-8, 2012
HICC, Hyderabad, India

http://www.serc.iisc.ernet.in/~viren/RASDAT12/

CALL FOR PAPERS
Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

Even as advances in CMOS technology come up against physical limits of material properties and lithography, raising many new challenges that must be overcome to ensure IC quality and reliability, there appears to be no obvious alternate technology that can replace End-of-Roadmap CMOS over the next decade. However, many reliability challenges from increasing defect rates, manufacturing variations, soft errors, wearout, etc. will need to be addressed by innovative new design and test methodologies if device scaling is to continue on track as per Moore’s Law to 10nm and beyond. The key objective of this annual workshop, planned to be held in conjunction with the International Conference on VLSI Design, is to provide an informal forum for vigorous creative discussion and debate of this area. The aim is to encourage the presentation and discussion of truly innovative and “out-of-the-box” ideas that may not yet have been fully developed for presentation at reviewed conferences to address these challenges. Additionally, the workshop invites embedded talks and tutorials on cutting edge topics related to reliability aware design of CMOS and hybrid nanotechnology systems.

Representative topics include, but are not limited to:

  • Design for test
  • Built-in self-test
  • ATPG and defect oriented test
  • Delay test
  • Low power test
  • Instruction-based self-test
  • On-line test methodology
  • Reliability of CMOS circuits
  • Self checker circuits
  • Self diagnosis methods
  • Fault tolerant micro-architecture
  • Self-healing system design
  • Energy and performance aware fault -tolerant micro-architectures
  • Device degradation and mitigation
  • System validation methodology
  • Secure system design
  • Design for reliability, dependability, and verifiability


Submissions

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Authors are invited to submit previously unpublished technical proposals. The proposals must be full papers not to exceed 6 pages. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and 6 to 7 keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address. Submit a copy of your proposal in PDF either online submission via workshop website http://www.serc.iisc.ernet.in/~viren/RASDAT12/

Submissions are due no later than October 21, 2011. Authors will be notified of the disposition of their presentation by November 15, 2011 Authors of accepted presentations must submit the final paper by December 1, 2011 for inclusion in the Workshop Proceedings, which will be provided to the attendees.

Key Dates

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Submission deadline: October 21, 2011
Notification of acceptance: November 15, 2011
Final copy deadline: December 1, 2011

Additional Information
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General Information

Adit Singh
Auburn University, Auburn, USA
E-mail: adsingh@auburn.edu
Tel: +1.334.644.1647
Fax: +1.334.844.1809

Virendra Singh
Indian Institute of Science, Bangalore, India
E-mail: viren@serc.iisc.ernet.in
Tel: +91.80.2293.3421
Fax: +91.80.2360.2648

Program Related Information

Rubin Parekhji
parekhji@ti.com
Erik Larsson
Erik.larsson@liu.se
Committees
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Organizing Committee

General Co-Chairs
Adit Singh (Auburn U., US)
Virendra Singh (IISc, IN)

General Vice Co-Chairs
Michiko Inoue (NAIST, JP)
Sreejit Chakravarty (LSI, US)

Program Co-Chairs
Erik Larsson (Linkoping U. SE)
Rubin Parekhji (TI, IN)

Program Vice Co-Chairs
Ilia Polian (Passau U., DE)
MS Gaur (MNIT, IN)

Organizing Committee Co-Chairs
Bhargab Bhattacharya (ISI, IN)
V. Kamakoti (IITM, IN)

Publication Chair
Vijay Laxmi (MNIT, IN)

Finance Co-Chair
Pradip Thaker (Beeceem, IN)
S. Ramakrishnan (WT, IN)

Publicity Chair
Susanta Chakravarty (BESU, IN)
Chia Yee Ooi (TUM, MY)

Local Arrangement Chair
TBD

Website Management Chair
Sushil Kabra (BSNL, IN)

Registration Chair
Jaynarayan Tudu (IISc, IN)
Arjun Chiluka (IISc, IN)

Steering Committee

K.K. Saluja (US) – Chair
J.A. Abraham (US)
V.D. Agrawal (US)
B. Al-Hashimi (UK)
B. Becker (DE)
A. Chatterjee (US)
H. Fujiwara (JP)
M. Fujita (JP)
E. Larsson (SE)
R. Parekhji (IN)
S.M. Reddy (US)
A.D. Singh (US)
V. Singh (IN)

Program Committee

TBD

For more information, visit us on the web at: http://www.serc.iisc.ernet.in/~viren/RASDAT12/

The 3rd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT 2012) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Joan FIGUERAS
UPC Barcelona Tech - Spain
Tel. +
E-mail figueras@eel.upc.edu

ITC GENERAL CHAIR
Doug YOUNG
- USA
Tel. +1-602-617-0393
E-mail doug0037@aol.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Athens
- Greece
Tel. +30-210-7275145
E-mail dgizop@di.uoa.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chen-huan.chiang@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
Krish CHAKRABARTY
Duke University - USA
Tel. +1-
E-mail krish@ee.duke.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chen-huan.chiang@alcatel-lucent.com

TECHNICAL ACTIVITIES
Patrick GIRARD
LIRMM – France
Tel.+33 467 418 629
E-mail patrick.girard@lirmm.fr

ASIA & PACIFIC
Kazumi HATAYAMA
NAIST - Japan
Tel. +81 743 72 5221
E-mail k-hatayama@is.naist.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com